The present invention relates to a logic verifying technique and a test-data generating method for logic circuits. More particularly, it relates to techniques which perform logic simulation or fault simulation for a synchronous sequential circuit including memory elements, at high speed by utilizing arithmetical units such as a vector computer or a parallel processor.
Heretofore, regarding a method wherein the logic simulation and fault simulation of a logic circuit are performed at high speed by utilizing a parallel arithmetic unit such as a vector computer, a fault simulation method which is based on an expanded parallel technique,i.e., a dynamic two-dimensional parallel technique for a combinational circuit has been known as stated in, for example, the Proceedings of the Society of Information Processing, Vol. 29, No. 5, pp. 522-528.
In the parallel arithmetic unit, a plurality of processes are executed in parallel at one time, thereby realizing an increased speed of computation. Accordingly, it is absolutely essential to contrive a data organization and processing steps with which the largest possible number of independent events can be collected and processed in parallel. Also, a method which processes a plurality of input patterns in parallel is effective for logic simulation or fault simulation. With the dynamic two-dimensional parallel technique mentioned above, the paralleling of processes is implemented for a plurality of patterns on the basis of the parallel technique. This technique is such that the logical values of the series of patterns stored in vector registers are subjected to logical operations at one time for the respective patterns independently of one another.
In executing the logical operation of a memory element such as a flip-flop, however, an output logical .value cannot be settled for a pattern to which the output logical value to the preceding pattern is held or kept unchanged. By way of example, in a case where, as illustrated in FIG. 9, a series of logical value patterns 903 are input to an R/S flip-flop 901 which operates in accordance with a truth table 902, `1` is set as the output value of the flip-flop to the first pattern. Then, the output value ought to be `1` to the second pattern as the actual operation of this flip-flop because the value to the preceding pattern is held. Since, however, the dynamic two-dimensional parallel technique executes the logical operations for the respective patterns at one time independently of one another, the logical value to the preceding pattern cannot be obtained for the logical operation to the second pattern, and hence, the output value cannot be settled. Accordingly, a synchronous sequential circuit including memory elements cannot be handled with this technique.